Modern microprocessors may utilize various logic circuitry to perform various logic operations. These logic operations may include the execution of various instructions carried out by functional blocks of the processor's logic circuitry. The instructions carried out by the processor may be of various types such as data processing instructions, computational instructions, storage instructions, as well as other information instructions. The operations and associated instructions may be carried out sequentially or in parallel and/or may be performed as part of a “pipeline” where multiple instructions are executed at multiple stages of a processor at the same time.
The operations and instructions performed by the processor may be susceptible to monitoring for reverse engineering purposes. For example, the processor may consume an amount of power during the execution of a logic operation and associated instruction. The monitoring of the processor's changing power consumption may enable identification of the logic operation being performed and may enable reverse engineering of code associated with the instruction that was performed.
This problem becomes more significant when the operations and instructions involve steps of a cryptographic algorithm used to secure data and other information. For example, the logic operations and associated instructions performed by a processor may involve steps of a cipher algorithm associated with an encryption standard such as the Advanced Encryption Standard (AES) or the Data Encryption Standard (DES) or a Rivest, Shamir, Aldeman (RSA) cryptosystem. Analysis of a processor's power consumption associated with cryptographic operations/instructions may reveal various cryptographic steps (e.g., steps involving cryptographic “keys”) which may result in the compromise of information security.
One such analysis may include the power monitoring techniques of Differential Power Analysis (DPA) that enable the identification of “keys” of cryptographic algorithms associated with various encryption standards. To illustrate, as part of a DPA attack on a processor, power consumptions for different instructions (e.g., cipher instructions) may be estimated and coupled with the monitoring of the processor's power consumption. The DPA attack may reveal the operations/instructions (e.g., cryptographic steps and/or keys) that are executed by functional blocks of the processor.
In traditional cryptographic devices, the possibility of a DPA attack has driven designers to use various techniques to conceal the power consumption required by each instruction and/or round(s) of the chosen cryptographic algorithm. To date, no technique has been discovered that can accurately obscure the power consumption associated with the operations/instructions of a processor as they are being executed. This has resulted in a need to accurate and timely concealment of the operations involved at each stage of the algorithm from a determined attacker.